IIT Madras hosts digital India RISC-V symposium
To facilitate collaboration between research institutions & stakeholders for next-gen chip design
IIT Madras has teamed up with the Union Ministry of Electronics and Information Technology (MeitY), RISC-V International and industry leaders, to host the second digital India RISC-V (DIR-V) symposium recently. The DIR-V Symposium 2025 is a crucial platform for defining India’s self-reliance in semiconductor technology, aligning with national initiatives such as ‘Digital India’, ‘Make in India’ and the ‘India Semiconductor Mission.’
This premier event brought together global and Indian experts, policymakers, start-ups, academia and industry pioneers to discuss the latest advancements in RISC-V-based processor design, open-source hardware innovations and India’s semiconductor roadmap. “Today, in almost every aspect of that technology ecosystem - whether it is the component, the device, the systems, segments of the economy that are embracing electronics and digital technologies or the software stacks that sit on all of it - all of this is getting ‘re-architectured’ and re-done,” said Rajeev Chandrasekhar, former Union Minister of State for Electronics and Information Technology.
Addressing the symposium earlier, Prof V Kamakoti, Director, IIT Madras, added, “RISC-V, being an open-source, extensible domain specific Instruction Set Architecture (ISA), has a great promise for us to design novel normative architectures and make it available to the startup industry who can in turn, customize them and make very efficient and effective domain specific SoCs (System-on-Chips).”
